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A Pipelined Multi-Core Machine with Operating System Support: Hardware Implementation and Correctness Proof

84,68 
84,68 
2025-07-31 84.6800 InStock
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Knygos aprašymas

This work is building on results from the book named ¿A Pipelined Multi-core MIPS Machine: Hardware Implementation and Correctness¿ by M. Kovalev, S.M. Müller, and W.J. Paul, published as LNCS 9000 in 2014. It presents, at the gate level, construction and correctness proof of a multi-core machine with pipelined processors and extensive operating system support with the following features: ¿ MIPS instruction set architecture (ISA) for application and for system programming ¿ cache coherent memory system ¿ store buffers in front of the data caches ¿ interrupts and exceptions ¿ memory management units (MMUs) ¿ pipelined processors: the classical five-stage pipeline is extended by two pipeline stages for address translation ¿ local interrupt controller (ICs) supporting inter-processor interrupts (IPIs) ¿ I/O-interrupt controller and a disk

Informacija

Autorius: Petro Lutsyk, Wolfgang J. Paul, Jonas Oberhauser,
Leidėjas: Springer Nature Switzerland
Išleidimo metai: 2020
Knygos puslapių skaičius: 644
ISBN-10: 3030432424
ISBN-13: 9783030432423
Formatas: Knyga minkštu viršeliu
Kalba: Anglų
Žanras: Mathematical theory of computation

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