There is continuous research to exploit the improved speed of scaled CMOS technologies in realizing high-speed analog-to-digital converters and SAR ADCs are one of the candidates which can significantly benefit from this technology scaling. Remarkable improvements have been recently reported on single-channel time-interleaved charge-based SAR ADCs to achieve sampling rates in the range of GS/s with excellent power effeciency but the challenge of driving a large sampling capacitor with high accuracy in a short sampling window is often not addressed. In this work, a high-speed current-mode DAC is replacing the commonly used charge-mode SC-DAC which alleviates the problem of driving a large input sampling capacitor in a short time. The proposed current-mode SAR ADC also uses a Gm stage which converts the input voltage to a current which is then processed in a current-based binary search algorithm SAR loop. In comparison to the conventional SC-SAR ADC structures, the sampling capacitor size is smaller than the total capacitance of the comparable SC-SAR ADCs. Moreover, low-impedance DAC-reference voltages which are essential for SC-DAC are removed by using this approach.
| Autorius: | Abdelrahman Elkafrawy, Maurits Ortmanns, |
| Leidėjas: | LAP LAMBERT Academic Publishing |
| Išleidimo metai: | 2018 |
| Knygos puslapių skaičius: | 132 |
| ISBN-10: | 613992801X |
| ISBN-13: | 9786139928019 |
| Formatas: | Knyga minkštu viršeliu |
| Kalba: | Anglų |
| Žanras: | Electronics and communications engineering |
Parašykite atsiliepimą apie „Concept and Design of a High Speed Current Mode Based SAR ADC“
